SLG47503 datasheet(116/191 Pages) DIALOG

116 / 191 page

Datasheet

16-Jul-2021

CFR0011-120-00

Revision 2.0

116 of 191

SLG47502/03

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

15.4.6 I2C Serial Reset Command

If I2C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including

configuration of all macrocells, and all connections provided by the Connection Matrix. This is implemented by setting

register [17:16] I2C reset bit to “1”, which causes the device to re-enable the Power-On Reset (POR) sequence, including the

reload of all register data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has

taken place, the contents of register [17:16] will be set to “0” automatically. Figure 105 illustrates the sequence of events for this

reset function.

15.4.7 I2C Additional Options

When Output latching during I2C write, register [1425] = 1 allows all PINs output value to be latched until I2C write is done. It will

protect the output change due to configuration process during I2C write in case multiple register bytes are changed. Inputs and

internal macrocells retain their status during I2C write.

If the user sets GPIO0 and GPIO1 function to a selection other than SDA and SCL, all access via I2C will be disabled.

Note: Any write commands that come to the device via I2C that are not blocked, based on the protection bits, will change the

contents of the RAM register bits that mirror the NVM bits. These write commands will not change the NVM bits themselves, and

a POR event will restore the register bits to original programmed contents of the NVM.

See Section 17 for detailed information on all registers.

15.4.8 Reading Counter Data via I2C

The current count value in all counters in the device can be read via I2C.

15.4.9 I2C Byte Write Bit Masking

The I2C macrocell inside SLG47502/03 supports masking of individual bits within a byte that is written to the RAM memory space.

This function is supported across the entire RAM memory space. To implement this function, the user performs a Byte Write

Command (see Section 15.4.1 for details) on the I2C Byte Write Mask Register (address 0F6H) with the desired bit mask pattern.

This sets a bit mask pattern for the target memory location that will take effect on the next Byte Write Command to this register

byte. Any bit in the mask that is set to “1” in the I2C Byte Write Mask Register will mask the effect of changing that particular bit

in the target register, during the next Byte Write Command. The contents of the I2C Byte Write Mask Register are reset (set to

Figure 105: Reset Command Timing

Control Byte

Word Address

Control

Code

Block

Address

Write bit

ACK

Acknowledge

bit

Start

bit

ACK

Data

Stop

bit

Acknowledge

bit

SDA LINE

Bus Activity

Acknowledge

bit

ACK

Reset-bit register output

DFF output gated by stop signal

Internal POR for core only

Internal Reset bit

by I2C Stop Signal

Not used, set to 0

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