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SLG47503 Datasheet(PDF) 128 Page - Dialog Semiconductor |
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SLG47503 Datasheet(HTML) 128 Page - Dialog Semiconductor |
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128 / 191 page ![]() Datasheet 16-Jul-2021 CFR0011-120-00 Revision 2.0 128 of 191 © 2021 Dialog Semiconductor SLG47502/03 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary 24 292 Multi-function0 OUT42: IN0 of MLT0_LUT4_1 or Clock Input of DFF14 or Delay0 Input (or Counter0 nRST Input) 293 294 295 25 296 297 298 OUT43: IN1 of MLT0_LUT4_1 or nRST of DFF14 or Delay0 Input (or Counter0 nRST Input or External Clock Source) 299 300 301 302 303 26 304 OUT44: IN2 of IN2 of MLT0_LUT4_1 or nSET of DFF14 or KEEP of Delay0/Counter0 305 306 307 308 309 310 OUT45: IN3 of MLT0_LUT4_1 or Data Input of DFF14 or UP of Delay0/ Counter0 311 27 312 313 314 315 316 Multi-function1 OUT46: IN0 of MLT1_LUT3_10 or Clock Input of DFF15 or Delay1 Input (or Counter1 nRST Input) 317 318 319 28 320 321 322 OUT47: IN1 of MLT1_LUT3_10 or nRST(nSET) of DFF15 or Delay1 Input (or Counter1 nRST Input or External Clock Source) 323 324 325 326 327 Table 37: Register Map (Continued) Address Signal Function Register Bit Definition Byte Register Bit |
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