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SLG47503 Datasheet(PDF) 124 Page - Dialog Semiconductor |
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SLG47503 Datasheet(HTML) 124 Page - Dialog Semiconductor |
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124 / 191 page ![]() Datasheet 16-Jul-2021 CFR0011-120-00 Revision 2.0 124 of 191 © 2021 Dialog Semiconductor SLG47502/03 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary E 112 LUT3_1 & DFF4 OUT12: IN1 of LUT3_1 or Data Input of DFF4 or Data Input of Shift_Reg4 113 114 115 116 117 118 OUT13: IN2 of LUT3_1 or nRST (nSET) of DFF4 or nRST(nSET) of Shift_Reg4 119 F 120 121 122 123 124 LUT3_2 & DFF5 OUT14: IN0 of LUT3_2 or Clock Input of DFF5 or Clock Input of Shift_Reg5 125 126 127 10 128 129 130 OUT15: IN1 of LUT3_2 or Data Input of DFF5 or Data Input of Shift_Reg5 131 132 133 134 135 11 136 OUT16: IN2 of LUT3_2 or nRST(nSET) of DFF5 or nRST(nSET) of Shift_Reg5 137 138 139 140 141 142 LUT3_3 & DFF6 OUT17: IN0 of LUT3_3 or Clock Input of DFF6 or Clock Input of Shift_Reg6 143 12 144 145 146 147 148 OUT18: IN1 of LUT3_3 or Data Input of DFF6 or Data Input of Shift_Reg6 149 150 151 13 152 153 154 OUT19: IN2 of LUT3_3 or nRST(nSET) of DFF6 or nRST(nSET) of Shift_Reg6 155 156 157 158 159 Table 37: Register Map (Continued) Address Signal Function Register Bit Definition Byte Register Bit |
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