PCA5010 datasheet(49/112 Pages) PHILIPS

49 / 112 page

1998 Nov 02

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5010

Table 42 Description of the DMD1 bits

6.17.4

CLOCK RECOVERY CONTROL REGISTER (DMD2)

The clock recovery control register DMD2 contains the control bits for enabling the clock recovery function and setting

its mode.

Whenever the clock recovery function is enabled (DMD2.7 = 1) the positive edge of the synchronized SYMCLK signal

will force a SymClk interrupt through the IRQ1.3 request flag after [B2, B1 and B0] received bits (see Table 50).

Table 43 Clock Recovery Control Register (DMD2, SFR address EEH)

Table 44 Description of the DMD2 bits

6.17.5

DEMODULATOR DATA REGISTER (DMD3)

The demodulator data register DMD3 contains the (demodulated) recovered received symbols.

Table 45 Demodulator Data Register (DMD3, SFR address EFH)

BIT

SYMBOL

FUNCTION

DMD1.7

ENA

enable averaging function/offset calculation

DMD1.6

AVG6

7-bit value indicating the offset value of the demodulator. This is an indication of the LO

offset frequency and will be used to determine the AFC output voltage. For coding see

Table 37.

DMD1.5

AVG5

DMD1.4

AVG4

DMD1.3

AVG3

DMD1.2

AVG2

DMD1.1

AVG1

DMD1.0

AVG0

76543210

ENC

−

TEST

BIT

SYMBOL

FUNCTION

DMD2.7

ENC

enable clock recovery function

DMD2.6

−

not used

DMD2.5

bypass demodulator ﬁlter

DMD2.4

−

not used

DMD2.3

TEST

reserved, should always be logic 0

DMD2.2

select number of bits per interrupt:

DMD2.1

If LEV = 0 then 000 = 1-bit, 001 = 2-bit to 111 = 8-bit

DMD2.0

If LEV = 1 then 00X = 2-bit, 01X = 4-bit, 10X = 6-bit, 11X = 8-bit

76543210

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