PCF50732 datasheet(13/64 Pages) PHILIPS

13 / 64 page

1999 May 03

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

Fig.4 Power ramping timing characteristics (multislot mode).

(1) APE_DAC3: Analog Power Enable signal for the AUXDAC3.

handbook, full pagewidth

MGR995

trup

trim

trdo

tru

AUXDAC3

TXON

APE_DAC3(1)

ADDRESS

AUXDAC3

RAM

tim

trd

9.3.3

RECEIVER PATH BLOCK DESCRIPTION

9.3.3.1

Receive serial interface

The baseband serial interface sends the digital signal of

the receive path to a digital signal processor. It also takes

the digital bitstream from the digital signal processor and

transmits it via the baseband CODEC.

The baseband reception and transmission are active in

bursts. A normal burst has a length of 548

µs. The frame

rate of bursts is 4.615 ms. Using a normal traffic channel,

one burst for each frame is transmitted and two bursts are

received. To save as much power as possible, the transmit

path and the receive path of the PCF50732 are in

power-up mode only during the transmission or reception

bursts respectively.

The power-up of the receive section is controlled via the

RXON pin or RXON bit. When RXON is driven HIGH, the

receive section recovers from power-down and the output

clock BIOCLK is activated. After a settling delay of 52

µs

(ZIF mode, analog circuitry + decimation filter settling

time), BOEN goes LOW to transfer the first 12-bit

I and Q words. The settling time is only 26

µs in NZIF

mode.

Bits are clocked out of the PCF50732 by the falling edge,

and clocked into the DSP by the rising edge of BIOCLK.

In normal bursts 148 I/Q pairs are read from the

PCF50732.

When RXON goes LOW, the last pair of I and Q values will

be sampled and transferred to the baseband processor

(both I and Q components). BIOCLK stops after additional

16 BIOCLK cycles. The receive path is powered down

again. In power-down the BIOCLK output is put in 3-state

and the BOEN output is HIGH.

The output format is 2

× 12-bit I/Q (twos complement).

Transmission occurs MSB first, I followed by Q. The serial

clock signal BIOCLK will run at 6.5 MHz, or 13 MHz in the

NZIF mode. Figure 6 shows the timing of the BSI data

reception.

An automatic offset compensation mechanism is provided

in order to achieve the required performance. This

mechanism will short the receive (RX) inputs internally and

measure the resulting offset value. This offset value will be

subtracted from all subsequent I/Q output words.

The offset inherent to the device can thereby be reduced

to a few millivolts. Default value for both I- and Q-offset is

zero.

PCF50732 Datasheet(PDF) 13 Page - NXP Semiconductors

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