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AD3552R Datasheet(PDF) 31 Page - Analog Devices |
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AD3552R Datasheet(HTML) 31 Page - Analog Devices |
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31 / 59 page  Data Sheet AD3541R THEORY OF OPERATION analog.com Rev. A | 31 of 59 When using single instruction mode, every CRC code in an SPI frame uses 0xA5 as the seed value to prevent stuck at fault conditions for Address 0x00. When using streaming mode, the first CRC code in an SPI frame also uses 0xA5 as the seed value, but subsequent CRC codes in the same frame are calculated using the least significant byte of the register address being accessed in the SPI transaction as the seed value. Because enabling the CRC in single SPI (classic) mode requires that the SDO pin shifts out the CRC calculated by the AD3541R, the transaction must respect the limitations of a read operation, which is that DDR is disabled. In dual SPI modes, the CRC is appended at the end of the byte or multibyte register transaction but the CRC is generated only by the controller (write) or by the AD3541R (read), as shown in Figure 88. When CRC error detection is enabled, do not use streaming mode, including looping, if the range of registers being addressed includes unused or reserved registers. Figure 88. Dual SPI Transaction with CRC |
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