AD3552R datasheet(27/59 Pages) AD

27 / 59 page

Data Sheet

AD3541R

THEORY OF OPERATION

analog.com

Rev. A | 27 of 59

Multibyte Registers

Some AD3541R registers consist of 2 or 3 bytes of data stored

in adjacent addresses and are referred to as multibyte registers.

Multibyte registers end with a 16B or 24B suffix when they are 2

bytes or 3 bytes, respectively.

When writing to a multibyte register of the AD3541R, all bytes must

be transferred in a single SPI transaction. For this reason, the

STRICT_REGISTER_ACCESS bit in the INTERFACE_ CONFIG_C

multibyte register is attempted on a per byte basis, the register con-

tents are not updated and the PARTIAL_REGISTER_ACCESS bit

in the INTERFACE_ STATUS_A register is set. A write transaction

to a multibyte register of the AD3541R takes effect after the 24th or

16th SCLK edge of the data phase, which shifts in the last bit of the

Figure 80. Multibyte Register Write with Ascending Addressing

Figure 81. Multibyte Register Read with Descending Addressing

The address of a multibyte register always depends on the

ADDR_DIRECTION bit in the INTERFACE_CONFIG_A register

(see the Address Direction section for more details). With descend-

ing addressing, the first byte accessed in the data phase must

be the most significant byte of the multibyte register, and each

subsequent byte corresponds to the data in the next lower address.

With ascending addressing, the first byte accessed in the data

phase must be the least significant byte of the multibyte register,

and each subsequent byte corresponds to the data in the next

higher address.

Multibyte registers can be read in a single SPI transaction or each

byte can be addressed separately. If an SPI read transaction to

a multibyte register is attempted on a per byte basis, the PARTI-

AL_REGISTER_ACCESS bit in the INTERFACE_ STATUS_A reg-

ister is set. For example, the VENDOR_ID register is 2 bytes long,

and the addresses of its least significant byte and most significant

byte are 0x0C and 0x0D, respectively. Figure 80 and Figure 81

show write and read transactions to a multibyte register (2 bytes)

for address ascending and descending mode, respectively. See the

Address Direction section for more information on selecting address

descending (auto-decrementing) or ascending (auto-incrementing).

Address Direction

The address direction option is used to control whether the register

address is set to automatically increment (address ascending) or

decrement (address descending) when transferring multiple bytes

of data in a single data phase (for example, when accessing

multibyte registers, as shown in Figure 80 and Figure 81, or when

accessing multiple registers with streaming mode, as shown in

Figure 83).

Address direction is selected with the ADDR_DIRECTION bit in

the INTERFACE_CONFIG_A register. If ADDR_DIRECTION is set

to 0, the address decrements after each byte is accessed. If

ADDR_DIRECTION is set to 1, the address increments after each

byte is accessed.

When accessing multibyte registers, use descending addresses to

shift in the most significant byte first.

Multibyte registers from Address 0x29 onwards can only be ac-

cessed in descending mode.

Single Instruction Mode

When the SINGLE_INSTRUCTION bit in the INTERFACE_CON-

FIG_B register is set to 1, streaming mode is disabled, and single

instruction mode is enabled. In single instruction mode, the data

phase only contains data for a single register, and each data phase

must be followed by a new instruction phase, even if CS remains

low. Single instruction mode allows the digital host to quickly read

from and write to registers with nonadjacent addresses in a single

SPI frame, whereas streaming mode only allows either reading or

writing to contiguous registers without pulsing CS high to initiate a

new instruction phase.

Figure 82 shows an example of an SPI transaction in single instruc-

tion mode with the following register accesses:

►

Sets the output range.

►

Enables the output stage.

►

Reads the CHIP_TYPE register.

Figure 82. Single Instruction Mode Register Access Example with Address Descending

AD3552R Datasheet(PDF) 27 Page - Analog Devices

AD3552R Datasheet(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL