AD3552R datasheet(54/59 Pages) AD

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Data Sheet

AD3541R

REGISTERS

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Rev. A | 54 of 59

Table 41. Bit Descriptions for DAC_PAGE_16B

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

DAC_PAGE

DAC Page Data. Following a write to this register, the DAC code loaded into this register is

copied into the DAC register if the SEL_CH0 bit is set in the CH_SELECT_16B register.

0x0

R/W

Channel Select for Page Registers, Fast Mode

Address: 0x2F, Reset: 0x00, Name: CH_SELECT_16B

This register is provided for compatibility with multichannel chips of this family.

Table 42. Bit Descriptions for CH_SELECT_16B

Bits

Bit Name

Settings

Description

Reset

Access

[7:1]

RESERVED

Reserved.

0x0

SEL_CH0

Select Channel 0. When this bit is set, data written to the INPUT_PAGE_16B register is

copied to the CH0_INPUT_16B register and data written to the DAC_PAGE_16B register is

copied to the CH0_DAC_16B register.

0x0

R/W

0 No operation.

1 Copy to corresponding register in Channel 0.

Input Page Register, Fast Mode

Address: 0x30, Reset: 0x0000, Name: INPUT_PAGE_16B

This register is provided for compatibility with multichannel chips of this family.

Table 43. Bit Descriptions for INPUT_PAGE_16B

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

INPUT_PAGE

Input Page Data. Following a write to this register, the DAC code loaded into this register

is copied into the input register if the SEL_CH0 bit is set in the CH_SELECT_16B

0x0

R/W

Software LDAC Register, Fast Mode

Address: 0x32, Reset: 0x00, Name: SW_LDAC_16B

This register is used to trigger a data transfer between the input register and the DAC register. It is the software equivalent of pulsing the LDAC

line low.

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