AD3552R datasheet(5/59 Pages) AD

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Data Sheet

AD3541R

SPECIFICATIONS

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Rev. A | 5 of 59

Table 2. (Continued)

Parameter1

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Output Voltage Noise Density

173

nV/√Hz

f = 1 kHz, no load on VREF

167

nV/√Hz

f = 10 kHz, no load on VREF

Capacitive Load Stability2

4.7

µF

Load Regulation

µV/mA

At 25°C

Output Current Load Capability

±8

Line Regulation

142

µV/V

At 25°C

REFERENCE INPUT

Reference Current

μA

Reference Input Range2

VREF

2.4

2.5

2.6

Reference Input Impedance

MΩ

LOGIC INPUTS

Input Current

−1

µA

Per pin

Input Low Voltage

VIL

0.35 ×

VLOGIC

Input High Voltage

VIH

0.65 ×

VLOGIC

Pin Capacitance

LOGIC OUTPUTS

Output Low Voltage

VOL

0.20 ×

VLOGIC

ISINK = 100 μA

Output High Voltage

VOH

0.80 ×

VLOGIC

ISOURCE = 100 μA

Pin Capacitance

POWER REQUIREMENTS

VLOGIC Pin

1.1

1.8

1.89

VLOGIC Current

ILOGIC

7.5

µA

VIH = VLOGIC × 0.9, VIL = VLOGIC × 0.1

VLOGIC Dynamic Current

ILOGIC_DYNAMIC

3.2

SCLK = 66 MHz, dual SPI DDR, VIH = VLOGIC × 0.65, VIL

= VLOGIC × 0.35

DVDD Pin

1.71

1.8

1.89

DVDD Current

IDVDD

0.5

0.8

DVDD Dynamic Current

IDVDD_DYNAMIC

AD3541R-16, SCLK = 66 MHz, dual SPI DDR

AD3541R-12, SCLK = 66 MHz, dual SPI DDR

AVDD Pin

4.75

5.25

AVDD Current

IDD

AVDD Power-Down Current

IDD

0.6

After reset, DACs powered down

AVDD Reset Current

IDD

120

µA

RESET asserted

PVDD Pin

4.75

10.6

PVDD Current

IPVDD

4.5

10 V range full scale, load current not included

PVDD Power-Down Current

IPVDD

μA

Channel power-down bit set

PVSS Pin

PVDD −

10.6

PVSS Current6

IPVSS

3.8

±5 V range zero scale, load current not included

PVSS Power-Down Current

IPVSS

μA

Channel power-down bit set

Recommended Headroom and Footroom

200

See Figure 51

1 See the Terminology section.

2 Guaranteed by design and characterization, not production tested.

3 Measured at zero code.

4 See the Output Voltage Spans section.

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