AD3552R datasheet(35/59 Pages) AD

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Data Sheet

AD3541R

THEORY OF OPERATION

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Rev. A | 35 of 59

Table 13. DAC Update Modes

SPI Mode

LDAC Pin

Synchronous

Notes

Dual and Single SPI

CH0_INPUT

Falling edge

Yes

LDAC mask applied, HW_LDAC register.

Dual and Single SPI

CH0_INPUT

High

Write to SW_LDAC triggers the update.

Dual and Single SPI

CH0_INPUT

Low

Output updates automatically.

Dual and Single SPI

CH0_DAC

Not applicable

Output updates immediately.

Dual and Single SPI

DAC_PAGE

Not applicable

Page mask applied, according to

CH_SELECT register. Output updates

immediately.

Dual and Single SPI

INPUT_PAGE

Not applicable

Page mask applied, according to

CH_SELECT register. Data copied to

input register.

POWER-DOWN

Each of the two DAC coresThe DAC core in the AD3541R can be

disabled to reduce power consumption when the channel is not in

use. Control is performed using the CH0_DAC_POWERDOWN bit

in the POWERDOWN_CONFIG register. The DAC core is powered

down after reset and becomes active on the first update.

In addition, the internal TIA can be disabled by setting the

CHx_CHANNEL_POWERDOWN bit in the POWERDOWN_CON-

FIG register. The TIA is powered up by default after reset.

RESET

The AD3541R implements three different ways to reset the device.

All three methods trigger the same reset procedure internally, ex-

cept for the difference explained in the Software Reset section.

Power-On Reset

The device integrates a power-on reset (POR) circuit that monitors

AVDD and DVDD. Whenever AVDD falls below 4 V or DVDD falls

below 1.3 V, an internal reset pulse is generated. This circuit

ensures that the chip is correctly initialized at power-up or after a

power dip.

RESET Pin

A low level on the RESET pin sets the chip in default mode,

clearing the values of all registers, setting the VOUT0 outputs to

0 V, and keeping the SPI lines in high impedance. When the

RESET line is released (returns high), the device starts executing

the initialization procedure that can take up to 100 ms (t18 time).

After reset, the DAC core is in power-down mode and the VOUT

outputs are still at 0 V.

During reset, the internal transimpedance amplifier is still powered

up and it may produce some glitch in the VOUT signal, depending on

the sequencing of the supplies.

Software Reset

The device can be reset from the SPI interface by setting

the SW_RESET_MSB and SW_RESET_LSB bits in the INTER-

FACE_CONFIG_A register. The main difference between the soft-

ware reset and the hardware reset using the RESET pin is that the

former does not affect the INTERFACE_CONFIG_A register. The

SW_RESET_MSB and SW_RESET_LSB bits clear after the reset

operation has concluded.

ERROR DETECTION

The AD3541R can detect abnormal conditions both in the ana-

log and digital domains. These errors are reported in the INTER-

FACE_STATUS_A and ERR_STATUS registers. The list of the

errors mapped to the ERR_ALARM_MASK register and its cor-

responding source is shown in Table 14. The errors listed in

Table 14 can assert the ALERT pin if it is not masked in the

ERR_ALARM_MASK register. The ALERT pin is also asserted after

reset and in case of initialization failure.

The error bits in the INTERFACE_STATUS_A and ERR_STATUS

registers are sticky and keep their value until cleared with a write 1

operation. That is, to clear an error bit, write 1 on that specific bit

location.

Table 14. Alarm Mask Register and Corresponding Error Source

Bit Number

Alarm Mask Register Bit Name

Error Source Register Name

Error Source Bit Name

REF_RANGE_ALARM_MASK

ERR_STATUS

REF_RANGE_ERR_STATUS

CLOCK_COUNT_ALARM_MASK

INTERFACE_STATUS_A

CLOCK_COUNTING_ERROR

MEM_CRC_ALARM_MASK

ERR_STATUS

MEM_CRC_ERR_STATUS

SPI_CRC_ERR_ALARM_MASK

INTERFACE_STATUS_A

INVALID_OR_NO_CRC

WRITE_TO_READ_ONLY_ALARM_MASK

INTERFACE_STATUS_A

WRITE_TO_READ_ONLY_REGISTER

PARTIAL_REGISTER_ACCESS_ALARM_MASK

INTERFACE_STATUS_A

PARTIAL_REGISTER_ACCESS

REGISTER_ADDRESS_INVALID_ALARM_MASK INTERFACE_STATUS_A

REGISTER_ADDRESS_INVALID

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