AD3552R datasheet(53/59 Pages) AD

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Data Sheet

AD3541R

REGISTERS

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Rev. A | 53 of 59

Table 38. Bit Descriptions for CH0_OUTPUT_RANGE (Continued)

Bits

Bit Name

Settings

Description

Reset

Access

[3:0]

CH0_OUTPUT_RANGE_SEL

Channel 0 Output Range Select. The user can select which voltage

output range is desired.

0x0

R/W

000 0 V to 2.5 V range. Requires RFB1_0 connection.

001 0 V to 5 V range. Requires RFB1_0 connection.

010 0 V to 10 V range. Requires RFB2_0 connection.

011 −5 V to +5 V range. Requires RFB2_0 connection.

100 −2.5 V to +7.5 V range. Requires RFB2_0 connection.

Hardware LDAC Mask Register, Fast Mode

Address: 0x28, Reset: 0x00, Name: HW_LDAC_16B

This register controls the masking of the external LDAC signal to latch data into the DAC register.

Table 39. Bit Descriptions for HW_LDAC_16B

Bits

Bit Name

Settings

Description

Reset

Access

[7:1]

RESERVED

Reserved.

0x0

HW_LDAC_MASK_CH0

Hardware LDAC Mask for Channel 0. This bit controls the latching of data

into the DAC register when the LDAC signal is asserted.

0x0

R/W

0 Data is latched in DAC Register 0 when the LDAC pin is asserted.

1 LDAC signal masked for Channel 0. DAC register is not updated when

LDAC is asserted.

DAC Register for Channel 0, Fast Mode

Address: 0x29, Reset: 0x0000, Name: CH0_DAC_16B

This register contains the data currently played on DAC Channel 0.

Table 40. Bit Descriptions for CH0_DAC_16B

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

DAC_DATA0

Channel 0 DAC Data.

0x0

R/W

DAC Page Register, Fast Mode

Address: 0x2D, Reset: 0x0000, Name: DAC_PAGE_16B

This register is provided for compatibility with multichannel chips of this family.

AD3552R Datasheet(PDF) 53 Page - Analog Devices

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