AD3552R datasheet(57/59 Pages) AD

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Data Sheet

AD3541R

REGISTERS

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Input Page Register, Precision Mode

Address: 0x42, Reset: 0x000000, Name: INPUT_PAGE_24B

This register is provided for compatibility with multichannel chips of this family.

Table 50. Bit Descriptions for INPUT_PAGE_24B

Bits

Bit Name

Settings

Description

Reset

Access

[23:8]

INPUT_PAGE

Input Page Data. Following a write to this register, the DAC code loaded into this register

is copied into the input register if the SEL_CH0 bit is set in the CH_SELECT_24B

0x0

R/W

[7:0]

RESERVED

Reserved.

0x0

Software LDAC Register, Precision Mode

Address: 0x45, Reset: 0x00, Name: SW_LDAC_24B

This register is used to trigger a data transfer between the input register and the DAC register. It is the software equivalent of pulsing the LDAC

line low.

Table 51. Bit Descriptions for SW_LDAC_24B

Bits

Bit Name

Settings

Description

Reset

Access

[7:1]

RESERVED

Reserved.

0x0

SW_LDAC_CH0

Software LDAC for Channel 0. Setting this bit transfers contents from the

CH0_INPUT_24B register to the CH0_DAC_24B register. This bit automatically resets

after being written.

0x0

0 No operation.

1 Load DAC 0.

Input Register for Channel 0, Precision Mode

Address: 0x46, Reset: 0x000000, Name: CH0_INPUT_24B

This register contains the data to be transferred to the DAC register using one of the various trigger options, hardware LDAC, software LDAC,

or automatic transfer.

Table 52. Bit Descriptions for CH0_INPUT_24B

Bits

Bit Name

Settings

Description

Reset

Access

[23:8]

INPUT_DATA0

Channel 0 Input Data.

0x0

R/W

[7:0]

RESERVED

Reserved.

0x0

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