AD3552R datasheet(11/59 Pages) AD

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Data Sheet

AD3541R

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 11 of 59

Figure 9. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

DVDD

Digital Core Power Supply. 1.8 V ± 5%.

VLOGIC

Digital Interface Power Supply. 1.2 V to 1.8 V.

Chip Select, Active Low Logic Input. This is the frame synchronization signal for the input data.

SCLK

Serial Clock Input.

SDI/SDIO0

DI/O

Serial Data Input in Classic SPI Mode.

Serial Bidirectional Input/Output Bit 0 in Dual SPI Mode.

SDO/SDIO1

DI/O

Serial Data Output in Classic SPI Mode.

Serial Bidirectional Input/Output Bit 1 in Dual SPI Mode.

LDAC

Load DAC, Active Low Logic Input. LDAC can be operated in two modes: synchronous or asynchronous. Pulsing this pin low

causes the DAC register to update if the input register has new data. If this pin is tied permanently low, the DAC automatically

updates when new data is written to the input register.

RESET

Asynchronous Reset Input. Active low logic input. When RESET is low, all registers are reset to their default values and the activity

on the digital interface is ignored. The AD3541R incorporates a power-on reset (POR) circuit. If this pin is not used, it must be tied

to VLOGIC.

ALERT

Alert Pin. Active low logic output. This pin is driven low if an alert condition is detected and it is not masked by the corresponding bit

in the mask register. This pin has an internal configurable pull-up resistor.

10, 26

AGND

Analog Ground Reference. It is recommended to connect DGND and AGND to the same ground plane under the device.

11 to 15, 28 DNC

Do Not Connect. Leave these pins floating.

PVDD

Positive Supply Voltage for Output Amplifier.

AVDD

Analog Power Supply. 5 V ± 5%.

VREF

AI/O

Voltage Reference, 2.5 V. Input when using the external reference, and output or floating when using the internal reference.

CVREF

AI/O

Decoupling Capacitor for Internal Reference, Optional.

VOUT0

AI/O

Analog Output Voltage for Channel 0.

RFB4_0

AI/O

Hardware Gain Selection for Channel 0, Gain = 4.

RFB2_0

AI/O

Hardware Gain Selection for Channel 0, Gain = 2.

RFB1_0

AI/O

Hardware Gain Selection for Channel 0, Gain = 1.

CAP0

AI/O

Amplifier Feedback Capacitor for Channel 0. Connect a capacitor (NP0 recommended) between this pin and VOUT0 to adjust the

amplifier bandwidth.

PVSS

Negative Rail for Output Amplifier.

DGND

Digital Ground Reference. It is recommended to connect DGND and AGND to the same ground plane under the device.

1 S = supply, DI = digital input, DO = digital output, and AI/O = analog input/output.

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