AD3552R datasheet(46/59 Pages) AD

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Data Sheet

AD3541R

REGISTERS

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Rev. A | 46 of 59

Transfer Configuration Register

Address: 0x0F, Reset: 0x00, Name: TRANSFER_REGISTER

This register configures the SPI mode used to transfer data and enables looping over the same register section when streaming data.

Table 30. Bit Descriptions for TRANSFER_REGISTER

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

MULTI_IO_MODE

Controls the SPI.

0x0

R/W

00 Single SPI.

01 Dual SPI.

[5:3]

RESERVED

Reserved.

0x0

STREAM_LENGTH_KEEP_VALUE

This bit controls the reset of the LENGTH bit field value in the

STREAM_MODE register.

0x0

R/W

0 LENGTH bit field is reset to 0 at the end of the transaction.

1 LENGTH bit field keeps the same value.

[1:0]

RESERVED

Reserved.

0x0

Interface Configuration C Register

Address: 0x10, Reset: 0x23, Name: INTERFACE_CONFIG_C

Additional interface configuration settings.

Table 31. Bit Descriptions for INTERFACE_CONFIG_C

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

CRC_ENABLE

CRC Enable. This field is written to enable/disable the use of the

CRC error detection on the interface (when the device is in register

mode). The CRC_ENABLE_B bits must also be written with the

inverted value of the CRC_ENABLE bits in the same SPI write

transaction for the CRC status to be changed.

0x0

R/W

00 CRC disabled.

01 CRC enabled.

STRICT_REGISTER_ACCESS

Access Mode to Multibyte Registers. This bit is read only. Register

write transactions to multibyte registers must include data for

each of its individual bytes for the register to be updated. Failure

0x1

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