AD3552R datasheet(56/59 Pages) AD

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Data Sheet

AD3541R

REGISTERS

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DAC Register for Channel 0, Precision Mode

Address: 0x38, Reset: 0x000000, Name: CH0_DAC_24B

This register contains the data currently played on DAC Channel 0.

Table 47. Bit Descriptions for CH0_DAC_24B

Bits

Bit Name

Settings

Description

Reset

Access

[23:8]

DAC_DATA0

Channel 0 DAC Data.

0x0

R/W

[7:0]

RESERVED

Reserved.

0x0

DAC Page Register, Precision Mode

Address: 0x3E, Reset: 0x000000, Name: DAC_PAGE_24B

This register is provided for compatibility with multichannel chips of this family.

Table 48. Bit Descriptions for DAC_PAGE_24B

Bits

Bit Name

Settings

Description

Reset

Access

[23:8]

DAC_PAGE

DAC Page Data. Following a write to this register, the DAC code loaded into this register is

copied into the DAC register if the SEL_CH0 bit is set in the CH_SELECT_24B register.

0x0

R/W

[7:0]

RESERVED

Reserved.

0x0

Channel Select for Page Registers, Precision Mode

Address: 0x41, Reset: 0x00, Name: CH_SELECT_24B

This register is provided for compatibility with multichannel chips of this family.

Table 49. Bit Descriptions for CH_SELECT_24B

Bits

Bit Name

Settings

Description

Reset

Access

[7:1]

RESERVED

Reserved.

0x0

SEL_CH0

Select Channel 0. When this bit is set, data written to the INPUT_PAGE_24B register is

copied to the CH0_INPUT_24B register and data written to the DAC_PAGE_24B register is

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