AD3552R datasheet(48/59 Pages) AD

48 / 59 page

Data Sheet

AD3541R

REGISTERS

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Rev. A | 48 of 59

Table 32. Bit Descriptions for INTERFACE_STATUS_A (Continued)

Bits

Bit Name

Settings

Description

Reset

Access

0 Clock count error not detected.

1 Clock count error detected.

RESERVED

Reserved.

0x0

INVALID_OR_NO_CRC

Invalid CRC or No CRC Received. This is set when the

master fails to send a CRC or when the device calculates

and checks the CRC and finds its value is incorrect. This

error flag is write‑1‑to‑clear (when this error flag is set, it

can only be reset by writing a 1 to this bit).

0x0

R/W1C

0 CRC error not detected.

1 CRC error detected.

WRITE_TO_READ_ONLY_REGISTER

Write to Read-Only Register Attempted. This bit indicates

if the digital host attempts an SPI write to a register that

contains exclusively read only fields. This error flag is

write‑1‑to‑clear (when this error flag is set, it can only be

reset by writing a 1 to this bit).

0x0

R/W1C

0 No error.

1 Write to read-only register detected.

PARTIAL_REGISTER_ACCESS

Partial Register Access Error Flag. This bit is asserted

when there are not enough bytes of data in a transaction

addressed to a multibyte register. This error flag is

write‑1‑to‑clear (when this error flag is set, it can only

be reset by writing a 1 to this bit).

0x0

R/W1C

0 Partial access error not detected.

1 Partial access error detected.

REGISTER_ADDRESS_INVALID

read or write transaction was attempted on an invalid

this error flag is set, it can only be reset by writing a 1 to

this bit).

0x0

R/W1C

0 Invalid address error not detected.

1 Invalid address error detected.

Interface Configuration D Register

Address: 0x14, Reset: 0x04, Name: INTERFACE_CONFIG_D

This register contains miscellaneous configuration bits affecting SPI communication and electrical parameters of digital signals.

Table 33. Bit Descriptions for INTERFACE_CONFIG_D

Bits

Bit Name

Settings

Description

Reset

Access

RESERVED

Reserved.

0x0

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