AD3552R datasheet(7/59 Pages) AD

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Data Sheet

AD3541R

SPECIFICATIONS

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Rev. A | 7 of 59

Table 4. (Continued)

Parameter1, 2

Description

Min

Typ

Max

Unit

Test Conditions/Comments

1.1 < VLOGIC < 1.7

t10

SCLK sampling edge to LDAC falling edge

7.6

t11

LDAC pulse width low

7.6

t12

CS rising edge to SDO disabled

t13

LDAC rising edge to CS falling edge

t14

RESET pulse width low

t14 to t19 shown in Figure 8

t15

RESET pulse activation time

100

t16

VOUTx update from CHx_DAC register write

12.6

t17

VOUT update from LDAC falling edge

t184

Wait time before DAC register access

100

t195

Shutdown exit time

Update Rate

Dual SPI mode, DDR and streaming enabled, precision mode

MUPS6

Dual SPI mode, DDR and streaming enabled, fast mode

16.5

MUPS6

1 All input signals are specified with tR = tF = 1 ns/V (10% to 90%) and timed from a voltage level of (VIL + VIH)/2.

2 Guaranteed by design and characterization, not production tested.

3 The SCLK sampling edge refers to the SCLK edge where the data is read in (sampled).

4 Same timing must be expected at power-up from the instant that AVDD = 4 V or DVDD = 0.8 V.

5 Time required to exit power-down to normal mode.

6 MUPS is mega updates per second.

Timing Diagrams

Figure 2. Classic SPI Write Operation with Single Data Rate

Figure 3. Classic SPI Read Operation with Single Data Rate

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