AD3552R datasheet(52/59 Pages) AD

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Data Sheet

AD3541R

REGISTERS

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Rev. A | 52 of 59

Table 36. Bit Descriptions for ERR_STATUS (Continued)

Bits

Bit Name

Settings

Description

Reset

Access

bit corruption within the memory

map.

[3:1]

RESERVED

Reserved.

0x0

RESET_STATUS

Reset Occurred. This bit indicates

that the device has just completed

initialization following a reset. This

bit asserts the ALERT pin and it is

nonmaskable. Therefore, it must be

cleared right after initialization.

0x1

R/W1C

Power-Down Configuration Register

Address: 0x18, Reset: 0x00, Name: POWERDOWN_CONFIG

This register controls the individual power-down of the DAC channels.

Table 37. Bit Descriptions for POWERDOWN_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

RESERVED

Reserved.

0x0

CH0_DAC_POWERDOWN

Channel 0 DAC Power-Down.

0x0

R/W

0 Channel 0 DAC in normal operating mode.

1 Channel 0 DAC is in power-down mode.

[3:1]

RESERVED

Reserved.

0x0

CH0_CHANNEL_POWERDOWN

Channel 0 Output Amplifier Power-Down.

0x0

R/W

0 Channel 0 output amplifier is powered on.

1 Channel 0 output amplifier is in power-down mode.

Output Range Register

Address: 0x19, Reset: 0x00, Name: CH0_OUTPUT_RANGE

This register sets the output range of the DAC channels to one of the preconfigured ranges listed in Table 8. In addition to setting this register,

the corresponding RFBx_0 resistor must be connected to obtain the expected result.

Table 38. Bit Descriptions for CH0_OUTPUT_RANGE

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

RESERVED

Reserved.

0x0

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