AD3552R datasheet(6/59 Pages) AD

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Data Sheet

AD3541R

SPECIFICATIONS

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Rev. A | 6 of 59

5 Reference temperature coefficient is calculated as per the box method.

6 Measured as current sourced from the PVSS pin.

AC CHARACTERISTICS

AVDD = 5.0 V ± 5%, DVDD = 1.8 V ± 5%, 1.1 V ≤ VLOGIC ≤ 1.9 V, 4.75 V ≤ PVDD − PVSS ≤ 10.6 V, 4.75 V ≤ PVDD ≤ 10.6 V, −5.3 V ≤ PVSS ≤ 0 V,

and −40°C ≤ TA ≤ +105°C, unless otherwise noted.

Table 3.

Parameter1

Min

Typ

Max

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

100

2 V step, 0.1% error, 0 V to 5 V range

2 V step, 1% error, 0 V to 5 V range

60 mV step, 0.1% error, 0 V to 5 V range

60 mV step, 1% error, 0 V to 5 V range

Slew Rate

100

V/µs

Full-scale step, 0 V to 2.5 V range, −40 °C to +105°C

140

V/µs

Full-scale step, all other ranges, −40 °C to +105 °C

Digital-to-Analog Glitch Impulse

pV×s

0 V to 5 V range, ±1 LSB change around major carry

Digital Feedthrough

pV×s

50 MHz clock, RFB2_x

AC PSRR

1 kHz, RFB1_x

1 MHz, RFB1_x

Output Noise Spectral Density

nV/√Hz

DAC code = midscale, external reference, 10 kHz, RFB1_x

nV/√Hz

RFB2_x

Output Noise

3.8

µVRMS

DAC code = midscale, external reference, 1 Hz to 10 kHz, RFB1_x

7.6

µVRMS

RFB2_x

Total Harmonic Distortion (THD)

−105

AD3541R-16, 0 V to 5 V range, fOUT = 1 kHz

−101

AD3541R-16, fOUT = 10 kHz

−90

AD3541R-12, fOUT = 1 kHz to 10 kHz

−84

fOUT = 100 kHz

Spurious-Free Dynamic Range (SFDR)

−105

AD3541R-16, 0 V to 5 V range, fOUT = 1 kHz

−92

AD3541R-12

1 See the Terminology section.

TIMING CHARACTERISTICS

AVDD = 5.0 V ± 5%, DVDD = 1.8 V ± 5%, 1.1 V ≤ VLOGIC ≤ 1.9 V, 4.75 V ≤ PVDD − PVSS ≤ 10.6 V, 4.75 V ≤ PVDD ≤ 10.6 V, −5.3 V ≤ PVSS ≤ 0 V,

and −40°C ≤ TA ≤ +105°C, unless otherwise noted.

Table 4.

Parameter1, 2

Description

Min

Typ

Max

Unit

Test Conditions/Comments

fSCLK

SCLK frequency

MHz

SCLK cycle time

15.2

tSCLK/2

SCLK half period

7.6

CS falling edge to first SCLK rising edge

Last SCLK sampling edge3 to CS rising edge

CS falling edge from SCLK sampling edge ignored

CS rising edge to SCLK rising edge ignored

Minimum CS high time

Data setup time

Data hold time

SCLK falling edge to SDO data valid

1.7 < VLOGIC < 1.9

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