PM3350-SW datasheet(177/224 Pages) PMC

177 / 224 page

ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

175

DMCR_ch7en:

Active high enable for local MAC channel 7

DMCR_prden:

Active high enable for PCI read channel. Automatically set when a

set_transmit flip is performed on channel 8.

DMCR_pwren:

Active high enable for PCI write channel. Automatically set when a

set_transmit flip is performed on channel 9.

DMCR_pincen:

Active high enable for PCI increment channel. Automatically set when a

set_transmit flip is performed on channel 10.

DMCR_drst:

Active high reset for DMA logic. If this bit is set to a logic 1, the DMA

functional block is held in its reset state.

DMCR_lbk:

If this bit is a logic 1 the LBK output pin is asserted high to force the PHY

device into loopback mode.

DMCR_pci_rd:

If this bit is a logic 1 the out of packet buffers notification for the PCI read

channel will be suspended. If this bit is logic 0 during PCI reads if the free list

goes to zero(out of packet buffers) the RISC will be notified during the PCI

read channel interrupt.

DMCR_enhpcirdmode:

If this bit is a logic 0 the PCI read channel will read the entire packet buffers

worth of data over the PCI. If this bit is logic 1 the PCI read channel will run

in enhanced mode by reading across the PCI only the required data in the

packet buffer. This is done in the following manner. If the number of packet

buffers in the frame is greater than one (1) then it is expected that the first

packet buffer header of the frame to be formatted in the following manner:

Bits [31:24]

Bits [23:0]

Word 0

Packet Buffer Bytes

Packet Buffer Next

Pointer

Word 1

Last Packet Buffer Bytes

Don't Care

Word 0 contains the normal information for the PC read channel. Word 1 contains

the number of bytes in the last packet buffer in this frame.

PM3350-SW Datasheet(PDF) 177 Page - PMC-Sierra, Inc

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