C8051F360 datasheet(143/288 Pages) SILABS

143 / 288 page

Rev. 1.0

143

C8051F360/1/2/3/4/5/6/7/8/9

13.4. Flash Read Timing

On reset, the C8051F36x Flash read timing is configured for operation with system clocks up to 25 MHz. If

the system clock will not be increased above 25 MHz, then the Flash timing registers may be left at their

reset value.

For every Flash read or fetch, the system provides an internal Flash read strobe to the Flash memory. The

Flash read strobe lasts for one or two system clock cycles, based on the FLRT bits (FLSCL.4 and

FLSCL.5). If the system clock is greater than 25 MHz, the FLRT bit must be changed to the appropri-

ate setting. Otherwise, data read or fetched from Flash may not represent the actual contents of Flash.

When the Flash read strobe is asserted, Flash memory is active. When it is de-asserted, Flash memory is

in a low power state.

The recommended procedure for updating FLRT is:

Step 1. Select SYSCLK to 25 MHz or less.

Step 2. Disable the prefetch engine (CHPFEN = ‘0’ in CCH0CN register).

Step 3. Set the FLRT bits to the appropriate setting for the SYSCLK.

Step 4. Enable the prefetch engine (CHPFEN = ‘1’ in CCH0CN register).

SFR Definition 13.3.

Bits 7–6: UNUSED. Read = 00b. Write = don’t care.

Bits 5–4: FLRT: Flash Read Time.

These bits should be programmed to the smallest allowed value, according to the system

clock speed.

00: SYSCLK < 25 MHz.

01: SYSCLK < 50 MHz.

10: SYSCLK < 75 MHz.

11: SYSCLK < 100 MHz.

Bits 3–0: RESERVED. Read = 0000b. Must Write 0000b.

Important Note: When changing the FLRT bits to a lower setting (e.g. when changing from a

value of 11b to 00b), cache reads, cache writes, and the prefetch engine should be

disabled using the CCH0CN register (see SFR Definition 14.1).

SFR Page:

SFR Address:

0xB6

R/W

Reset Value

–

FLRT

Reserved Reserved Reserved Reserved 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

FLSCL: Flash Memory Control

C8051F360 Datasheet(PDF) 143 Page - Silicon Laboratories

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