C8051F360 datasheet(140/288 Pages) SILABS

140 / 288 page

C8051F360/1/2/3/4/5/6/7/8/9

140

Rev. 1.0

13.3. Flash Write and Erase Guidelines

Any system which contains routines which write or erase Flash memory from software involves some risk

that the write or erase routines will execute unintentionally if the CPU is operating outside its specified

operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-

fying code can result in alteration of Flash memory contents causing a system failure that is only recover-

able by re-Flashing the code in the device.

To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and

enabled as a reset source on C8051F36x devices for the Flash to be successfully modified. If either the

VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset will be gen-

erated when the firmware attempts to modify the Flash.

The following guidelines are recommended for any system that contains routines which write or erase

Flash from code.

13.3.1. VDD Maintenance and the VDD Monitor

1. If the system power supply is subject to voltage or current "spikes," add sufficient transient

protection devices to the power supply to ensure that the supply voltages listed in the Absolute

Maximum Ratings table are not exceeded.

2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot

meet this rise time specification, then add an external VDD brownout circuit to the /RST pin of

the device that holds the device in reset until VDD reaches VRST and re-asserts /RST if VDD

drops below VRST. Please see Table 12.1, “Reset Electrical Characteristics,” on page 134 for

more information on the VDD Monitor Threshold voltage (VRST).

3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as early

in code as possible. This should be the first set of instructions executed after the Reset Vector.

For 'C'-based systems, this will involve modifying the startup code added by the 'C' compiler.

See your compiler documentation for more details. Make certain that there are no delays in

software between enabling the VDD Monitor and enabling the VDD Monitor as a reset source.

Code examples showing this can be found in AN201, "Writing to Flash from Firmware", avail-

able from the Silicon Laboratories web site.

Note: On C8051F36x devices, both the VDD Monitor and the VDD Monitor reset source must

be enabled to write or erase Flash without generating a Flash Error Device Reset.

4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a

reset source inside the functions that write and erase Flash memory. The VDD Monitor enable

instructions should be placed just after the instruction to set PSWE to a '1', but before the

Flash write or erase operation instruction.

5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment

operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-

ple, "RSTSRC = 0x02" is correct, but "RSTSRC |= 0x02" is incorrect.

6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas

to check are initialization code which enables other reset sources, such as the Missing Clock

Detector or Comparator, for example, and instructions which force a Software Reset. A global

search on "RSTSRC" can quickly verify this.

C8051F360 Datasheet(PDF) 140 Page - Silicon Laboratories

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