C8051F360 datasheet(149/288 Pages) SILABS

149 / 288 page

Rev. 1.0

149

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 14.1. CCH0CN: Cache Control

Bit 7:

CHWREN: Cache Write Enable.

This bit enables the processor to write to the cache memory.

0: Cache contents are not allowed to change, except during Flash writes/erasures or cache

locks.

1: Writes to cache memory are allowed.

Bit 6:

CHRDEN: Cache Read Enable.

This bit enables the processor to read instructions from the cache memory.

0: All instruction data comes from Flash memory or the prefetch engine.

1: Instruction data is obtained from cache (when available).

Bit 5:

CHPFEN: Cache Prefetch Enable.

This bit enables the prefetch engine.

0: Prefetch engine is disabled.

1: Prefetch engine is enabled.

Bit 4:

CHFLSH: Cache Flush.

When written to a ‘1’, this bit clears the cache contents. This bit always reads ‘0’.

Bit 3:

CHRETI: Cache RETI Destination Enable.

This bit enables the destination of a RETI address to be cached.

0: Destinations of RETI instructions will not be cached.

1: RETI destinations will be cached.

Bit 2:

CHISR: Cache ISR Enable.

This bit allows instructions which are part of an Interrupt Service Routine (ISR) to be cached.

0: Instructions in ISRs will not be loaded into cache memory.

1: Instructions in ISRs can be cached.

Bit 1:

CHMOVC: Cache MOVC Enable.

This bit allows data requested by a MOVC instruction to be loaded into the cache memory.

0: Data requested by MOVC instructions will not be cached.

1: Data requested by MOVC instructions will be loaded into cache memory.

Bit 0:

CHBLKW: Block Write Enable.

This bit allows block writes to Flash memory from software.

0: Each byte of a software Flash write is written individually.

1: Flash bytes are written in groups of four (for code space writes).

SFR Page:

SFR Address:

0x84

R/W

Reset Value

CHWREN CHRDEN CHPFEN CHFLSH

CHRETI

CHISR

CHMOVC CHBLKW 11100110

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

C8051F360 Datasheet(PDF) 149 Page - Silicon Laboratories

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