C8051F360 datasheet(151/288 Pages) SILABS

151 / 288 page

Rev. 1.0

151

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 14.3. CCH0LC: Cache Lock Control

Bit 7:

CHPUSH: Cache Push Enable.

This bit enables cache push operations, which will lock information in cache slots using

MOVC instructions.

0: Cache push operations are disabled.

1: Cache push operations are enabled. When a MOVC read is executed, the requested 4-

byte segment containing the data is locked into the cache at the location indicated by

CHSLOT, and CHSLOT is decremented.

Note:No more than 30 cache slots should be locked at one time, since the entire cache will be unlocked

when CHSLOT is equal to 0.

Bit 6:

CHPOP: Cache Pop.

Writing a ‘1’ to this bit will increment CHSLOT and then unlock that location. This bit always

reads ‘0’. Note that Cache Pop operations should not be performed while CHSLOT =

11110b. “Pop”ing more Cache slots than have been “Push”ed will have indeterminate results

on the Cache performance.

Bit 5:

RESERVED. Read = 0b. Must Write 0b.

Bits 4–0: CHSLOT: Cache Slot Pointer.

These read-only bits are the pointer into the cache lock stack. Locations above CHSLOT are

locked, and will not be changed by the processor, except when CHSLOT equals 0.

SFR Page:

SFR Address:

0xD2

R/W

RRR

Reset Value

CHPUSH

CHPOP RESERVED

CHSLOT

00011111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

C8051F360 Datasheet(PDF) 151 Page - Silicon Laboratories

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