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C8051F360 Datasheet(PDF) 150 Page - Silicon Laboratories

Part # C8051F360
Description  Mixed Signal ISP Flash MCU Family
PDF  288 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F360 Datasheet(HTML) 150 Page - Silicon Laboratories

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C8051F360/1/2/3/4/5/6/7/8/9
150
Rev. 1.0
SFR Definition 14.2. CCH0TN: Cache Tuning
Bits 7–4: CHMSCTL: Cache Miss Penalty Accumulator (Bits 4–1).
These are bits 4-1 of the Cache Miss Penalty Accumulator. To read these bits, they must first
be latched by reading the CHMSCTH bits in the CCH0MA Register (See SFR Definition
14.4).
Bit 3:
CHALGM: Cache Algorithm Select.
This bit selects the cache replacement algorithm.
0: Cache uses Rebound algorithm.
1: Cache uses Pseudo-random algorithm.
Bit 2:
CHFIXM: Cache Fix MOVC Enable.
This bit forces MOVC writes to the cache memory to use slot 0.
0: MOVC data is written according to the current algorithm selected by the CHALGM bit.
1: MOVC data is always written to cache slot 0.
Bits 1–0: CHMSTH: Cache Miss Penalty Threshold.
These bits determine when missed instruction data will be cached.
If data takes longer than CHMSTH clocks to obtain, it will be cached.
SFR Page:
SFR Address:
F
0xC9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
CHMSCTL
CHALGM CHFIXM
CHMSTH
00000100
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0



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