C8051F360 datasheet(267/288 Pages) SILABS

267 / 288 page

Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules

Rev. 1.0

267

C8051F360/1/2/3/4/5/6/7/8/9

22.2.1. Edge-triggered Capture Mode

In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/

timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and

PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-

tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),

or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)

in PCA0CN is set to logic ‘1’ and an interrupt request is generated if CCF interrupts are enabled. The

CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine,

and must be cleared by software. If both CAPPn and CAPNn bits are set to logic ‘1’, then the state of the

Port pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge

caused the capture.

PCA0L

PCA0CPLn

PCA

Timebase

CEXn

Crossbar

Port I/O

PCA0H

Capture

PCA0CPHn

PCA Interrupt

PCA0CPMn

PCA0CN

Figure 22.4. PCA Capture Mode Diagram

Note: The signal at CEXn must be high or low for at least 2 system clock cycles to be recognized by the

hardware.

PWM16 ECOM CAPP CAPN MAT

TOG

PWM ECCF

Operation Mode

Capture triggered by positive edge on

CEXn

Capture triggered by negative edge on

CEXn

Capture triggered by transition on

CEXn

Software Timer

High Speed Output

Frequency Output

8-Bit Pulse Width Modulator

16-Bit Pulse Width Modulator

X = Don’t Care

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