 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
C8051F360 Datasheet(PDF) 276 Page - Silicon Laboratories |
|
|
|||||||||||||||||||||||||||||
C8051F360 Datasheet(HTML) 276 Page - Silicon Laboratories |
|
|
276 / 288 page  C8051F360/1/2/3/4/5/6/7/8/9 276 Rev. 1.0 22.4. Register Descriptions for PCA0 Following are detailed descriptions of the special function registers related to the operation of PCA0. SFR Definition 22.1. PCA0CN: PCA Control Bit 7: CF: PCA Counter/Timer Overflow Flag. Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vec- tor to the CF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit 6: CR: PCA0 Counter/Timer Run Control. This bit enables/disables the PCA0 Counter/Timer. 0: PCA0 Counter/Timer disabled. 1: PCA0 Counter/Timer enabled. Bit 5: CCF5: PCA0 Module 5 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit 4: CCF4: PCA0 Module 4 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit 3: CCF3: PCA0 Module 3 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit 2: CCF2: PCA0 Module 2 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit 1: CCF1: PCA0 Module 1 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Bit 0: CCF0: PCA0 Module 0 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. SFR Page: SFR Address: all pages 0xD8 (bit addressable) R/WR/WR/WR/WR/WR/WR/W R/W Reset Value CF CR CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
