C8051F360 datasheet(272/288 Pages) SILABS

272 / 288 page

C8051F360/1/2/3/4/5/6/7/8/9

272

Rev. 1.0

22.2.6. 16-Bit Pulse Width Modulator Mode

Each PCA0 module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare

module defines the number of PCA0 clocks for the low time of the PWM signal. When the PCA0 counter

matches the module contents, the output on CEXn is asserted high; when the counter overflows, CEXn is

asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA0 CCFn

match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the

PCA0CPMn register. For a varying duty cycle, CCFn should also be set to logic ‘1’ to enable match inter-

rupts. The duty cycle for 16-Bit PWM Mode is given by Equation 22.3.

Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/

Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit

to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.

Equation 22.3. 16-Bit PWM Duty Cycle

DutyCycle

65536 PCA0CPn

–

()

65536

-----------------------------------------------------

Using Equation 22.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is

0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.

PCA0CPLn

PCA0CPHn

Enable

PCA Timebase

000 0

PCA0CPMn

16-bit Comparator

CEXn

Crossbar

Port I/O

Overflow

SET

CLR

match

PCA0H

PCA0L

Figure 22.9. PCA 16-Bit PWM Mode

22.3. Watchdog Timer Mode

A programmable watchdog timer (WDT) function is available through the PCA Module 5. The WDT is used

to generate a reset if the time between writes to the WDT update register (PCA0CPH5) exceed a specified

limit. The WDT can be configured and enabled/disabled as needed by software.

With the WDTE bit set in the PCA0MD register, Module 5 operates as a watchdog timer (WDT). The

Module 5 high byte is compared to the PCA counter high byte; the Module 5 low byte holds the offset to be

used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some

PCA registers are restricted while the Watchdog Timer is enabled.

C8051F360 Datasheet(PDF) 272 Page - Silicon Laboratories

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