TMPR4938 datasheet(397/716 Pages) TOSHIBA

397 / 716 page

Chapter 11 Serial I/O Port

11-19

11.4.4 Status Change Interrupt Status Register 0 (SISCISR0)

0xF30C (Ch. 0)

Status Change Interrupt Status Register 1 (SISCISR1)

0xF40C (Ch. 1)

Reserved

: Type

: Initial value

Reserved

OERS CTSS RBRKD TRDY TXALS UBRKD

R/W0C

R/W0C : Type

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:6

⎯

Reserved

⎯

OERS

Overrun Error

Overrun Error Status (Default: 0)

This bit is immediately set to “1” when an overrun error is detected. This bit

is cleared when a “0” is written.

R/W0C

CTSS

CTS Status

CTS Terminal Status (Default: 0)

This field indicates the status of the CTS signal.

1: The CTS signal is High.

0: The CTS signal is Low.

RBRKD

Receiving Break

Receive Break (Default: 0)

This bit is set when a break is detected. This bit is automatically cleared

when a frame that is not a break is received.

1: Current status is Break.

0: Current status is not Break.

TRDY

Transmission

Data Empty

Transmit Ready (Default: 1)

This bit is set to “1” if at least one stage in the Transmit FIFO is free.

TXALS

Transmission

Complete

Transmit All Sent (Default: 1)

This bit is set to “1” if the Transmit FIFO and all transmission shift registers

are empty.

UBRKD

Break Detected

UART Break Detect (Default: 0)

This bit is set when a break is detected. Once set, this bit remains set until

cleared by writing a “0” to it.

R/W0C

Figure 11.4.4 Status Change Interrupt Status Register

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