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TMPR4938 Datasheet(PDF) 441 Page - Toshiba Semiconductor

Part # TMPR4938
Description  64-Bit TX System RISC TX49 Family
PDF  716 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4938 Datasheet(HTML) 441 Page - Toshiba Semiconductor

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Chapter 14 AC-link Controller
14-17
14.4.1 ACLC Control Enable Register
0xF700
This register is used to check the setting of various ACLC features and to enable them.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
MODIE
HLT
MODOE
HLT
Reserved
AUDIE
HLT
LFEEH
LT
CENTE
HLT
SURRE
HLT
AUDO
EHLT
R/W1S R/W1S
R/W1S R/W1S R/W1S R/W1S R/W1S
: Type
0
0
0
0
0
0
0
: Initial value
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODID
MA
MODO
DMA Reserved
AUDID
MA
LFEDM
A
CENTD
MA
SURR
DMA
AUDO
DMA
Reserved
RDYCLR MICSEL WRESET WAKEUP
LOW
PWR
ENLINK
R/W1S R/W1S
R/W1S R/W1S R/W1S R/W1S R/W1S
W1S
R/W1S R/W1S R/W1S R/W1S R/W1S
: Type
0
0
0
0
0
0
0
0
0
0
0
0
0
: Initial value
Bit
Mnemonic Field Name
Description
Read/Write
31:24
⎯
Reserved
⎯
MODIEHLT: Enable Modem Receive-data DMA Error Halt.
R/W1S
23
Enable Modem
Receive-data
DMA Error Halt
R
0: Indicates that MODIDMA error halt is disabled.
1: Indicates that MODIDMA error halt is enabled.
W1S
0: No effect
1: Enables MODIDMA error halt. When MODIDMA overrun
occurs, subsequent DMA will not be issued.
MODOEHLT: Enable Modem Transmit-data DMA Error Halt.
R/W1S
22
MODOEHLT Enable Modem
Transmit-data
DMA Error Halt
R
0: Indicates that MODODMA error halt is disabled.
1: Indicates that MODODMA error halt is enabled.
W1S
0: No effect
1: Enables MODODMA error halt. When MODODMA underrun
occurs, subsequent DMA will not be issued.
21
⎯
Reserved
⎯
AUDIEHLT: Enable Audio Receive-data DMA Error Halt.
R/W1S
20
AUDIEHLT
Enable Audio
Receive-data
DMA Error Halt
R
0: Indicates that AUDIDMA error halt is disabled.
1: Indicates that AUDIDMA error halt is enabled.
W1S
0: No effect
1: Enables AUDIDMA error halt. When AUDIDMA overrun occurs,
subsequent DMA request will not be issued.
LFEEHLT: Enable Audio LFE Transmit-data DMA Error Halt.
R/W1S
19
LFEEHLT
R
0: Indicates that LFEDMA error halt is disabled.
1: Indicates that LFEDMA error halt is enabled.
Enable Audio
LFE
Transmit-data
DMA Error Halt
W1S
0: No effect
1: Enables LFEDMA error halt. When LFEDMA underrun occurs,
subsequent DMA request will not be issued.
CENTEHLT: Enable Audio Center Transmit-data DMA Error Halt.
R/W1S
18
CENTEHLT
R
0: Indicates that CENTDMA error halt is disabled.
1: Indicates that CENTDMA error halt is enabled.
Enable Audio
Center
Transmit-data
DMA Error Halt
W1S
0: No effect
1: Enables CENTDMA error halt. When CENTDMA underrun
occurs, subsequent DMA request will not be issued.
Figure 14.4.1 ACCTLEN Register (1/3)



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