IMX95CEC datasheet(26/113 Pages) NXP

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The i.MX SoC has no VDD2H vs VDDQ sequencing requirements, but generally VDDQ must come up after VDD2H

to meet DRAM memory component specification.

NOTE

9. Turn on any 3.3 V supplies. This includes NVCC_XX I/O supplies that being operated at 3.3 V and VDD_USB_3P3.

This 3.3 V supply step may be simultaneous with the DDR VDD2H or DDR VDDQ supplies if desired.

NOTE

10. Turn on NVCC_SD2, if NVCC_SD2 is being used for a dynamically switchable 1.8/3.3 V SD card voltage (booting initially

at 3.3 V).

If NVCC_SD2 is operating at a fixed 1.8 V-only or 3.3 V-only voltlage in a give system, then it may power up at the

same time as other supplies of the same voltage.

NOTE

11. POR_B release (it should be asserted during the entire power-up sequence).

4.2.1 Power-up sequence

The power-up sequence is defined as follows:

Table 28. Power-up sequence

Symbol

Description

Min

Typ

Max

Unit

Condition

tPMIC_ON_Req

The time from when

NVCC_BBSM_1P8 reaches its

minimum operating range to

when the SoC begins to assert

PMIC_ON_REQ.

—

tON_DEB

The time from when

PMIC_ON_REQ reaches its

high-level output voltage (VOH)

to when VDD_SOC begins to

power-up.

—

(not shown in

timing diagram)

The time from when VDD_SOC

begins to power-up to when

VDD_ARM begins to power-up.

0.5

—

tstep_dig_0p8

The time from when the latter

of VDD_SOC or VDD_ARM

begins to power-up to when all

VDD_*_0P8 analog, PHY and

PLL supplies begin to power-up.

0.5

—

tstep_0p8_1p8

The time from when the final

VDD_*_0P8 analog, PHY and

PLL supply begins to power-up

to when 1.8 V supplies begin to

power-up.

0.2

0.25

—

tstep_1p8_ddr2h

The time from when the final

1.8V supply begins to power-

up to when the DDR VDD2H

supply begins to power-up.

0.4

0.5

—

Table continues on the next page...

NXP Semiconductors

IMX95CEC

i.MX 95 Applications Processors Data Sheet for Commercial Products

IMX95CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 11 November 2024

Preliminary - Subject to Change Without Notice

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