IMX95CEC datasheet(43/113 Pages) NXP

43 / 113 page

Table 45. SAI/I2S Target mode timing (25 MHz)...continued

Symbol

Description

Min

Typ

Max

Unit

Condition

S19

SAI_FS input assertion to

SAI_TXD output valid3 2

—

1. SAI4 pins multiplexed over ENET2 when operating at 3.3 V I/O supply, this parameter value is 9.75 ns.

2. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear.

S15

S13

S15

S17

S18

S15

S16

S14

S16

S11

S12

I2S_BCLK (input)

I2S_FS (output)

I2S_TXD

I2S_RXD

I2S_FS (input)

S19

Figure 14. SAI timing-Target mode

4.9.1.5 SAI I/O specifications

Table 46. SAI I/O specifications

Mode

Pins

Clock

Frequency

Output

Input

Controller Tx

Any SAI interface multiplexes

over ENET pins for a SAI

instance is in NETCMIX.

Any SAI interface does not

multiplex over ENET pins

for a SAI instance is not

in NETCMIX.

TXC

50 MHz

TXD

—

TXC

50 MHz

TXFS

—

Any SAI interface multiplexes

over ENET pins for a SAI

instance is not in NETCMIX.

TXC

25 MHz

TXD

—

Any SAI interface does not

multiplex over ENET pins for a

SAI instance is in NETCMIX.

TXC

25 MHz

TXFS

—

Any

TXC

25 MHz

—

TXFS

Controller Rx

Any

RXC

25 MHz

—

RXD

Table continues on the next page...

NXP Semiconductors

IMX95CEC

i.MX 95 Applications Processors Data Sheet for Commercial Products

IMX95CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 11 November 2024

Preliminary - Subject to Change Without Notice

43 / 113

IMX95CEC Datasheet(PDF) 43 Page - NXP Semiconductors

IMX95CEC Datasheet(HTML) 43 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL