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IMX95CEC Datasheet(PDF) 4 Page - NXP Semiconductors |
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IMX95CEC Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 113 page  Table 1. Feature summary...continued Subsystem Features — 4-channel — 4 external trigger sources — Generic 32-bit resolution timer — Periodical interrupt generation • 6x Timer/PWM modules (TPM) — Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 — 16-bit counter, support free-running counter or modulo counter mode, counting up or down — Includes 6 channels that can be configured for input capture, output compare, edge-aligned PWM mode, or center-aligned PWM mode • 2x Low-Power Timers (LPTMR) • 5x WatchDog modules (WDOG) • 1x System Counter (SYS_CTR) • 1x Timestamp Timer (TSTMR) • 1x General Purpose Timer (GPT) GPIO and Pin Multiplexing • General-purpose input/output (GPIO) modules with interrupt capability • Input/Output Multiplexing Controller (IOMUXC) to provide centralized pad control Analog • FRO Clock Generator (FRO_TUNER) • 2x Temperature Sensor (TEMPSENSE) • 16-channel, 12-bit Analog-to-Digital Converter (SAR_ADC) • 1x Trigger Mux (TRGMUX) to configure the trigger inputs for various peripherals Clocking • CCM • OSC • LPCG Safety • Integrated functional safety • Targeting ISO26262 ASIL-B and IEC61508 SIL2 compliance Security • Trusted Resource Domain Controller (TRDC) — Supports up to 16 resource domains • Arm TrustZone® (TZ) architecture • Secure and trusted access control • EdgeLock™ Secure Enclave Table continues on the next page... NXP Semiconductors IMX95CEC i.MX 95 Applications Processors Data Sheet for Commercial Products IMX95CEC All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Preliminary Data Sheet Rev. 2 — 11 November 2024 Preliminary - Subject to Change Without Notice 4 / 113 |
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