IMX95CEC datasheet(71/113 Pages) NXP

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Table 77. LPSPI DC electrical characteristics...continued

Symbol

Description

Min

Typ

Max

Unit

Condition

VIL

Input low voltage 1,2

—

0.3 x

VDDO

—

IIN/IOZ

Input/Output leakage current 2

-5

—

µA

—

VOH

Output high voltage 2

VDDO -

0.45

—

IOH = -2 mA at VDDO

min

VOL

Output lowvoltage 2

—

0.45

IOL = 2 mA at VDDO

min

1. The minimum VIL and maximum VI values are based on the respective minimum and maximum VDD values found in

Recommended Operating Conditions.

2. For recommended operating conditions, see Recommended Operating Conditions.

4.11.3.2 LPSPI Controller mode AC timing specifications

Table 78. LPSPI Controller mode AC timing specifications

Symbol

Description

Min

Typ

Max

Unit

Condition

fSCK

Frequency of LPSPI clock

root 1,2,3

—

MHz

—

fSCK

Frequency of LPSPI clock root 4 —

—

MHz

—

tSCK

SCK period 5

2 x

tperiph

—

tLead

Enable lead time

—

tperiph

—

tLag

Enable lag time

—

tperiph

—

tWSCK

Clock (SCK) high or low time

tSCK / 2

- 3

—

tSCK / 2

+ 3

—

tSU

Data setup time (inputs) 6

—

When operating at 3.3

V I/O supply, this

parameter value is 9

ns.

tHI

Data hold time (inputs) 6

—

Data valid (after SCK edge)

—

2.5

—

tHO

Data hold time (outputs)

-2.5

—

tRI/FI

Rise/Fall time input

—

tRO/FO

Rise/Fall time output

—

1. The clock driver in the LPSPI module for fperiph must guaranteed this limit is not exceeded.

2. Input timing assumes an input signal slew rate of 3 ns (20%/80%).

3. Output timing valid for maximum external load CL = 25 pF, which is assumed to be a load at the end of a 50 ohm,

unterminated, 5-inch microstrip trace on standard FR4 (3.3 pF/inch), (25-pF total with margin). For best signal integrity, the

series resistance in the transmission line should be equal to the selected RDSON of the I/O pad output driver.

4. In controller loopback mode when LPSPI_CFGR1[SAMPLE] bit is 1.

5. tperiph = 1000 / fperiph

6. If LPSPI_CFGR1[SAMPLE] bit is 1, the data setup time (inputs) / data hold time (inputs) specifications are same with the

one in Peripheral mode.

NXP Semiconductors

IMX95CEC

i.MX 95 Applications Processors Data Sheet for Commercial Products

IMX95CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 11 November 2024

Preliminary - Subject to Change Without Notice

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