IMX95CEC datasheet(41/113 Pages) NXP

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S10

I2S_MCLK (output)

I2S_BCLK (output)

I2S_FS (output)

I2S_FS (input)

I2S_TXD

I2S_RXD

Figure 13. SAI timing-Controller modes

4.9.1.2 SAI/I2S Controller mode timing (25 MHz)

Input timing assumes an input signal slew rate of 3 ns (20%/80%).

Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm,

unterminated, 5-inch microstrip trace on standard FR4 (3.3 pF/inch), (25-pF total with margin). For best signal integrity, the series

resistance in the transmission line should be equal to the selected RDSON of the I/O pad output driver.

Table 43. SAI/I2S Controller mode timing (25 MHz)

Symbol

Description

Min

Typ

Max

Unit

Condition

SAI_MCLK cycle time

—

SAI_MCLK pulse width high/low 40%

—

60%

MCLK

period

—

SAI_BCLK cycle time

—

SAI_BCLK pulse width high/low 40%

—

60%

BCLK

period

—

SAI_BCLK to SAI_FS output

valid

—

SAI_BCLK to SAI_FS output

invalid

-2

—

SAI_BCLK to SAI_TXD valid

—

SAI_BCLK to SAI_TXD invalid

-2

—

SAI_RXD/SAI_FS input setup

before SAI_BCLK 1

9.5

—

S10

SAI_RXD/SAI_FS input hold

after SAI_BCLK

—

1. SAI4 pins multiplexed over ENET2 when operating at 3.3 V I/O supply, this parameter value is 9.75 ns.

NXP Semiconductors

IMX95CEC

i.MX 95 Applications Processors Data Sheet for Commercial Products

IMX95CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 11 November 2024

Preliminary - Subject to Change Without Notice

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