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IMX95CEC Datasheet(PDF) 57 Page - NXP Semiconductors |
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IMX95CEC Datasheet(HTML) 57 Page - NXP Semiconductors |
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57 / 113 page ![]() Table 57. Ethernet management interface AC Timing specifications...continued Symbol Description Min Typ Max Unit Condition tMGCL MDC clock pulse width low 40 — 40 % — tMDKHDX MDC to MDIO output delay 2,3,4 Y x tenet_clk - 3 — Y x tenet_clk + 3 — NEG=0 tMDKHDX MDC to MDIO output delay 2,3,4 Y -tenet_clk — Y + tenet_clk — NEG=1 tMDDVKH MDIO to MDC input setup time 5 8 — — ns — tMDDXKH MDIO to MDC input hold time 0 — — ns — tRGTR Rise time (20%-80%) — — TBD ns — tRGTF Fall time (20%-80%) — — TBD ns — 1. This parameter is dependent on the Ethernet clock frequency. The MDIO_CFG [MDIO_CLK_DIV] field determines the MDC clock frequency. 2. For NEG=0: Y = ( 1+(2+6*EHOLD)*MDIO_HOLD ) For NEG=1: Y=MDIO_CLK_DIV even: MDC clk / 2 Y=MDIO_CLK_DIV odd: (MDC clk / 2) +/- tENET_CLK 3. tENET_CLK = 333 Mhz max. How to program ??? 4. MDIO timing is configurable by programming the EMDIO_CFG register fields. The default value of Y = 5. Y is the value determined by EMDIO_CFG[NEG], EMDIO_CFG[MDIO_HOLD], and MDIO[EHOLD]. The easiest way is to program NEG=1, then MDIO is driven at negative edge of MDC, satisfying both setup and hold time requirement of Ethernet PHY. 5. The setup time tMDDVKH is measured at a) 470pf load @ 1.8V in open-drain mode b) 300pf load @ 1.8V in push-pull mode MDC MDIO (input) MDIO (output) tMDC tMDCH tMDDVKH tMDDXKH tMDKHDX Figure 23. Ethernet management interface timing diagram 4.11.2.1.2 Ethernet management interface DC electrical characteristics at voltage rail =1.8V This table provides the EMI DC electrical characteristics Table 58. Ethernet management interface DC electrical characteristics at voltage rail =1.8V Symbol Description Min Typ Max Unit Condition VIH Input high voltage 0.7 x SUPPLY — — V — Table continues on the next page... NXP Semiconductors IMX95CEC i.MX 95 Applications Processors Data Sheet for Commercial Products IMX95CEC All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Preliminary Data Sheet Rev. 2 — 11 November 2024 Preliminary - Subject to Change Without Notice 57 / 113 |
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