IMX95CEC datasheet(36/113 Pages) NXP

36 / 113 page

1. Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10-pF load at the end of a 50 Ω ,

unterminated, 5-inch microstrip trace on standard FR4 (3.3 pF/inch), (25-pF total with margin). For best signal integrity, the

series resistance of the transmission line can be equal to the selected RDSON of the I/O pad output driver.

2. Input timing assumes an input signal slew rate of 3 ns (20%/80%).

3. 50 MHz frequency is for the JTAG debug interface. For boundary scan, the maximum TCK frequency is 10 MHz.

4. TDC = target frequency of JTAG

5. VM = mid-point voltage

Following figure depicts the JTAG test clock imput timing.

JTAG_TCK

(Input)

VIH

VIL

SJ1

SJ2

SJ3

Figure 9. Test Clock Input Timing Diagram

Following figure depicts the JTAG boundary scan timing.

JTAG_TCK

(Input)

Data

Inputs

Data

Outputs

Data

Outputs

Data

Outputs

VIH

VIL

Input Data Valid

Output Data Valid

SJ4

SJ5

SJ6

SJ7

SJ6

Figure 10. Boundary system (JTAG) timing diagram

Following figure depicts the JTAG test access port.

JTAG_TCK

(Input)

JTAG_TDI

(Input)

JTAG_TDO

(Output)

JTAG_TDO

(Output)

VIH

VIL

Input Data Valid

Output Data Valid

JTAG_TMS

SJ8

SJ9

SJ10

SJ11

SJ14

Figure 11. Test Access Port Timing Diagram

NXP Semiconductors

IMX95CEC

i.MX 95 Applications Processors Data Sheet for Commercial Products

IMX95CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 11 November 2024

Preliminary - Subject to Change Without Notice

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