IMX95CEC datasheet(39/113 Pages) NXP

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4.8.1 12-bit ADC electrical specifications

All ADC channels meet the 12-bit single-ended accuracy specifications.

4.8.1.1 SAR ADC

Table 41. SAR ADC

Symbol

Description

Min

Typ

Max

Unit

Condition

VADIN

ADC Input Voltage

VGND

—

VDDA

on or off channels

fADCK

ADC Conversion Clock

Frequency

—

MHz

—

Csample

Sample cycles

5.5

—

Ccompare

Fixed compare cycles

—

131.5

—

Cconversion

Clock conversion cycles

Cconvers

ion =

Csample

Ccompar

Cconvers

ion =

Csample

Ccompar

Cconvers

ion =

Csample

Ccompar

number

of cycles

—

CAD_INPUT

ADC Input Capacitance

—

ADC component

plus pad capacitance

(~2pF)

RAD_INPUT

ADC Input Series Resistance

—

1.25

kΩ

—

DNL

ADC Differential Non-linearity

—

±2

—

LSB

after calibration

INL

ADC Integral Non-linearity

—

±6

—

LSB

after calibration

RAS

Analog source resistance

—

KΩ

—

Bandgap

Output voltage ready time for

bandgap

—

µs

—

4.9 Audio

This section introduces the timing and electrical parameters about audio subsystem of I.MX 95 processor.

4.9.1 SAI switching specifications

This section provides the AC timings for the SAI in Controller (clocks driven) and Target (clocks input) modes. All timings are given

for non inverted serial clock polarity (SAI_TCR2[BCP] = 0, SAI_RCR2[BCP] = 0) and non inverted frame sync (SAI_TCR4[FSP]

= 0, SAI_RCR4[FSP] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by

inverting the clock signal (SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.

The DSE[5:0] = 001111 and FSEL1[1:0] = 11 are required drive settings to meet the timing.

The SAI4 pins muxed with ENET2 and the SAI4 pins muxed with XSPI1 are mutually exclusive. It does not support a use case

where some SAI4 pins are connected to ENET2 and other SAI4 pins are simultaneously connected to XSPI1.

SAI5 is supported entirely on SD3 or entirely on XSPI1 (but not multiplexed across both XSPI1 and SD3 pins). SAI5 is also

supported with some pins on SD3 and others on XSPI1, as long as the non-data signals (SYNCs and/or BCLKs) are on the one

interface (SD3 or XSPI1), and all TX_DATA pins are on the one interface (SD3 or XSPI1), and all RX_DATA pins are on the one

interface (SD3 or XSPI1).

NXP Semiconductors

IMX95CEC

i.MX 95 Applications Processors Data Sheet for Commercial Products

IMX95CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 11 November 2024

Preliminary - Subject to Change Without Notice

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