IMX95CEC datasheet(3/113 Pages) NXP

3 / 113 page

Table 1. Feature summary...continued

Subsystem

Features

Video Processors

• 4Kp60 H.265 and H.264 encode and decode

• 1x JPEG Encoder

• 1x JPEG Decoder

Display Controller (up to 3

simultaneous displays)

• For 3 simultaneous displays (1x MIPI-DSI + 2x LVDS), both LVDS displays

must have same resolution and timing.

• 1x 350 MHz MIPI-DSI (4-lane, 2.5 Gbps/lane) supporting 4kp30 or 3840 x

1440p60

• 2x 1080p60 LVDS Tx (2x 4-lane or 1x 8-lane)

• 16 kByte of SRAM, but it is available for other SoC usage when not using for 2D

blitter purposes

Camera and ISP

• MIPI-CSI and ISP (2x 4-lane, 2.5 Gbps/lane) with PHY (one mux'd with DSI)

• Up to 1x 4Kp60 fps (if one MIPI CSI is enabled), 2x 4Kp30, 4x 1080p60, or 8x

1080p30

• Up to 8x cameras with MIPI virtual channels

• 96 kByte of SRAM, but it is available for other SoC usage when not using for

ISP purposes.

Audio

• 5x Synchronous Audio Interfaces (SAI)

• 17-lane I2S TDM (32-bit at 768 kHz frequency)

• SPDIF Rx and SPDIF Tx

• 8-channel PDM Microphone Interface (MICFIL)

• 2 x Medium Quality Sound (MQS)

Connectivity

• 2x PCIe Gen 3.0 (1-lane)

• 1x USB3.0 Type C with PHY

• 1x USB2.0 with PHY

• 2x 1 Gbps Ethernet ports with Time Sensitive Networking (TSN) capabilities

• 1x 10 Gbps Ethernet port with Time Sensitive Networking (TSN) capabilities

• IEEE 1588 for sync; and EEE

• 5x CAN-FD

• 2x 32-pin FLEXIO interfaces (bus or serial I/O)

Low Speed

Communication Peripherals

• 8x UART

Timer and PWMs

• 2x Low Power Periodical Interrupt Timers (LPIT)

Table continues on the next page...

NXP Semiconductors

IMX95CEC

i.MX 95 Applications Processors Data Sheet for Commercial Products

IMX95CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 11 November 2024

Preliminary - Subject to Change Without Notice

3 / 113

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