ADC3421 datasheet(16/80 Pages) TI2

16 / 80 page

ADC3421, ADC3422, ADC3423, ADC3424

SBAS673A – JULY 2014 – REVISED OCTOBER 2015

www.ti.com

7.12 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN)

All digital inputs support 1.8-V and

VIH

High-level input voltage

1.3

3.3-V CMOS logic levels

All digital inputs support 1.8-V and

VIL

Low-level input voltage

0.4

3.3-V CMOS logic levels

RESET, SDATA, SCLK,

VHIGH = 1.8 V

µA

High-level input

PDN

IIH

current

SEN(1)

VHIGH = 1.8 V

µA

RESET, SDATA, SCLK,

VLOW = 0 V

µA

Low-level input

PDN

IIL

current

SEN

VLOW = 0 V

µA

DIGITAL INPUTS (SYSREFP, SYSREFM)

VIH

High-level input voltage

1.3

VIL

Low-level input voltage

0.5

Common-mode voltage for SYSREF

0.9

DIGITAL OUTPUTS (CMOS Interface, SDOUT)

VOH

High-level output voltage

DVDD – 0.1

DVDD

VOL

Low-level output voltage

0.1

DIGITAL OUTPUTS (LVDS Interface)

VODH

High-level output differential voltage

With an external 100-

Ω termination

280

350

460

VODL

Low-level output differential voltage

With an external 100-

Ω termination

–460

–350

–280

VOCM

Output common-mode voltage

1.05

(1)

SEN has an internal 150-k

Ω pullup resistor to AVDD. SPI pins (SEN, SCLK, SDATA) can be driven by 1.8 V or 3.3 V CMOS buffers.

7.13 Timing Requirements: General

Typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum

and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C.

MIN

TYP

MAX

UNIT

Aperture delay

1.24

1.44

1.64

Aperture delay matching between two channels of the same device

±70

Aperture delay variation between two devices at same temperature and supply voltage

±150

Aperture jitter

130

fS rms

Time to valid data after exiting standby power-down mode

200

µs

Wake-up time:

Time to valid data after exiting global power-down mode

450

µs

(in this mode, both channels power down)

Clock

2-wire mode (default)

cycles

ADC latency(1):

Clock

1-wire mode

cycles

tSU_SYSREF

Setup time for SYSREF referenced to input clock rising edge

1000

SYSREF reference time:

tH_SYSREF

Hold time for SYSREF referenced to input clock rising edge

100

(1)

Overall latency = ADC latency + tPDI.

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