ADC3421 datasheet(70/80 Pages) TI2

70 / 80 page

ADC34xx

Analog

Input

Routing

Sampling

Clock

Routing

Digital

Output

Routing

ADC3421, ADC3422, ADC3423, ADC3424

SBAS673A – JULY 2014 – REVISED OCTOBER 2015

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12 Layout

12.1 Layout Guidelines

The ADC342x EVM layout can be used as a reference layout to obtain the best performance. A layout diagram

of the EVM top layer is provided in Figure 189. Some important points to remember during laying out the board

are:

1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the

package level. To minimize crosstalk onboard, the analog inputs must exit the pin out in opposite directions,

as shown in the reference layout of Figure 189 as much as possible.

2. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to

minimize coupling between them. This configuration is also maintained on the reference layout of Figure 189

as much as possible.

3. Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, the digital

output traces must not be kept parallel to the analog input traces because this configuration can result in

coupling from digital outputs to analog inputs and degrade performance. All digital output traces to the

receiver [such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)]

must be matched in length to avoid skew among outputs.

4. At each power-supply pin (AVDD and DVDD), keep a 0.1-µF decoupling capacitor close to the device. A

separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF

capacitors can be kept close to the supply source.

12.2 Layout Example

Figure 189. Typical Layout of the ADC342x Board

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Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424

ADC3421 Datasheet(PDF) 70 Page - Texas Instruments