ADC3421 datasheet(5/80 Pages) TI2

5 / 80 page

ADC3421, ADC3422, ADC3423, ADC3424

www.ti.com

SBAS673A – JULY 2014 – REVISED OCTOBER 2015

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Analog supply voltage range, AVDD

–0.3

2.1

Digital supply voltage range, DVDD

–0.3

2.1

INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM

–0.3

min (1.9, AVDD + 0.3)

CLKP, CLKM

–0.3

AVDD + 0.3

Voltage applied to

input pins

SYSREFP, SYSREFM

–0.3

AVDD + 0.3

SCLK, SEN, SDATA, RESET, PDN

–0.3

3.9

Operating free-air, TA

–40

Temperature

Operating junction, TJ

125

ºC

Storage, Tstg

–65

150

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±2000

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

(1)

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

SUPPLIES

AVDD

Analog supply voltage range

1.7

1.8

1.9

DVDD

Digital supply voltage range

1.7

1.8

1.9

ANALOG INPUT

For input frequencies < 450 MHz

VID

Differential input voltage

VPP

For input frequencies < 600 MHz

VIC

Input common-mode voltage

VCM ± 0.025

CLOCK INPUT

Input clock frequency

Sampling clock frequency

15(2)

125(3)

MSPS

Sine wave, ac-coupled

0.2

1.5

Input clock amplitude (differential)

LPECL, ac-coupled

1.6

VPP

LVDS, ac-coupled

0.7

Input clock duty cycle

35%

50%

65%

Input clock common-mode voltage

0.95

DIGITAL OUTPUTS

Maximum external load capacitance

CLOAD

3.3

from each output pin to GND

RLOAD

Single-ended load resistance

100

(1)

After power-up, use only the RESET pin to reset the device for the first time; see the Register Initialization section for details.

(2)

See Table 3 for details.

(3)

With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS.

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