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ADC3421 Datasheet(PDF) 59 Page - Texas Instruments |
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ADC3421 Datasheet(HTML) 59 Page - Texas Instruments |
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59 / 80 page ![]() ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.6.1.15 Register 27h (address = 27h) Figure 161. Register 27h 7 6 5 4 3 2 1 0 CLK DIV 0 0 0 0 0 0 R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 24. Register 27h Field Descriptions Bit Field Type Reset Description 7-6 CLK DIV R/W 0h These bits select the internal clock divider for the input sampling clock. 00 = Divide-by-1 01 = Divide-by-1 10 = Divide-by-2 11 = Divide-by-4 5-0 0 W 0h Must write 0. 9.6.1.16 Register 11Dh (address = 11Dh) Figure 162. Register 11Dh 7 6 5 4 3 2 1 0 0 0 0 0 0 0 HIGH IF MODE0 0 W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 25. Register 11Dh Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 HIGH IF MODE0 Set the HIGH IF MODE[7:0] bits together to 1111. Improves HD3 by a couple of dB for IF > 100 MHz. 0 0 W 0h Must write 0. 9.6.1.17 Register 122h (address = 122h) Figure 163. Register 122h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 DIS CHOP CHA 0 W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 26. Register 122h Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 DIS CHOP CHA R/W 0h This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc 0 0 W 0h Must write 0. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 59 Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 |
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