ADC3421 datasheet(42/80 Pages) TI2

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CLKP

CLKM

0.1 F

Device

100 W

0.1 F

TypicalLVPECL

ClockInput

150 W

CLKP

CLKM

0.1 F

100 W

Device

0.1 F

TypicalLVDS

ClockInput

CLKP

CLKM

0.1 F

Device

0.1 F

Differential

Sine-Wave

ClockInput

ADC3421, ADC3422, ADC3423, ADC3424

SBAS673A – JULY 2014 – REVISED OCTOBER 2015

www.ti.com

9.3 Feature Description

9.3.1 Analog Inputs

The ADC342x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing

symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input swing.

The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-

Ω source driving 50-Ω

termination between INP and INM).

9.3.2 Clock Input

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with

little or no difference in performance between them. The common-mode voltage of the clock inputs is set to

0.95 V using internal 5-k

Ω resistors. The self-bias clock inputs of the ADC342x can be driven by the transformer-

coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in

Figure 132, Figure 133, and Figure 134. See Figure 135 for details regarding the internal clock buffer.

NOTE: RT = termination resistor, if necessary.

Figure 132. Differential Sine-Wave Clock Driving

Figure 133. LVDS Clock Driving Circuit

Circuit

Figure 134. LVPECL Clock Driving Circuit

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Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424

ADC3421 Datasheet(PDF) 42 Page - Texas Instruments

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