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ADC3421 Datasheet(PDF) 41 Page - Texas Instruments |
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ADC3421 Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 80 page  CLKP CLKM INBP INBM Configuration Registers Common Mode VCM DA1P DA1M DB1P DB1M DA0P DA0M DB0P DB0M Digital Encoder and Serializer SYSREFP SYSREFM Divide by 1,2,4 INAP INAM 12-Bit ADC Digital Encoder and Serializer INDP INDM 12-Bit ADC INCP INCM 12-Bit ADC PLL 12-Bit ADC FCLKP FCLKM DCLKP DCLKM Bit Clock Frame Clock DC1P DC1M DD1P DD1M DC0P DC0M DD0P DD0M Digital Encoder and Serializer Digital Encoder and Serializer ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9 Detailed Description 9.1 Overview The ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to- digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports a serial low-voltage differential signaling (LVDS) interface in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. 9.2 Functional Block Diagram Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 41 Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 |
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