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ADC3421 Datasheet(PDF) 61 Page - Texas Instruments

Part # ADC3421
Description  ADC342x Quad-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converter
PDF  80 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADC3421 Datasheet(HTML) 61 Page - Texas Instruments

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ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com
SBAS673A – JULY 2014 – REVISED OCTOBER 2015
9.6.1.21 Register 222h (address = 222h)
Figure 167. Register 222h
7
6
5
4
3
2
1
0
0
0
0
0
0
0
DIS CHOP CHD
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 30. Register 222h Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0.
1
DIS CHOP CHD
R/W
0h
This bit disables the chopper.
Set this bit to shift the 1/f noise floor at dc.
0 = 1/f noise floor is centered at fS / 2 (default)
1 = Chopper mechanism is disabled; 1/f noise floor is centered
at dc
0
0
W
0h
Must write 0.
9.6.1.22 Register 234h (address = 234h)
Figure 168. Register 234h
7
6
5
4
3
2
1
0
0
0
DIS DITH CHD
0
DIS DITH CHD
0
0
0
W-0h
W-0h
R/W-0h
W-0h
R/W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 31. Register 234h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0.
5
DIS DITH CHD
R/W
0h
Set this bit with bits 1 and 0 of register 01h.
00 = Default
11 = Dither is disabled for channel D. In this mode, SNR
typically improves by 0.2 dB at 70 MHz.
4
0
W
0h
Must write 0.
3
DIS DITH CHD
R/W
0h
Set this bit with bits 1 and 0 of register 01h.
00 = Default
11 = Dither is disabled for channel D. In this mode, SNR
typically improves by 0.2 dB at 70 MHz.
2-0
0
W
0h
Must write 0.
Copyright © 2014–2015, Texas Instruments Incorporated
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Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424



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