ADC3421 datasheet(52/80 Pages) TI2

52 / 80 page

ADC3421, ADC3422, ADC3423, ADC3424

SBAS673A – JULY 2014 – REVISED OCTOBER 2015

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9.6.1 Serial Register Description

9.6.1.1 Register 01h (address = 01h)

Figure 147. Register 01h

DIS DITH CHA

DIS DITH CHB

DIS DITH CHC

DIS DITH CHD

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 9. Register 01h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

DIS DITH CHA

R/W

These bits enable or disable the on-chip dither. Control this bit

along with bits 5 and 3 of register 134h.

00 = Default

11 = Dither is disabled for channel A. In this mode, SNR typically

improves by 0.2 dB at 70 MHz.

5-4

DIS DITH CHB

R/W

These bits enable or disable the on-chip dither. Control this bit

along with bits 5 and 3 of register 434h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.2 dB at 70 MHz.

3-2

DIS DITH CHC

R/W

These bits enable or disable the on-chip dither. Control this bit

along with bits 5 and 3 of register 534h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.2 dB at 70 MHz.

1-0

DIS DITH CHD

R/W

These bits enable or disable the on-chip dither. Control this bit

along with bits 5 and 3 of register 234h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.2 dB at 70 MHz.

9.6.1.2 Register 03h (address = 03h)

Figure 148. Register 03h

ODD EVEN

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 10. Register 03h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Must write 0.

ODD EVEN

R/W

This bit selects the bit sequence on the output wires (in 2-wire

mode only).

0 = Bits 0, 1, 2, and so forth appear on wire-0; bits 7, 8, 9, and

so forth appear on wire-1.

1 = Bits 0, 2, 4, and so forth appear on wire-0; bits 1, 3, 5, and

so forth appear on wire-1.

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