ADC3421 datasheet(57/80 Pages) TI2

57 / 80 page

ADC3421, ADC3422, ADC3423, ADC3424

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SBAS673A – JULY 2014 – REVISED OCTOBER 2015

9.6.1.11 Register 0Fh (address = 0Fh)

Figure 157. Register 0Fh

CUSTOM PATTERN[3:0]

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 19. Register 0Fh Field Descriptions

Bit

Field

Type

Reset

Description

7-4

CUSTOM PATTERN[3:0]

R/W

These bits set the 12-bit custom pattern (bits 3-0) for all

channels.

3-0

Must write 0.

9.6.1.12 Register 13h (address = 13h)

Figure 158. Register 13h

LOW SPEED ENABLE

W-0h

R/W-0h

W-0h

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 20. Register 13h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

Must write 0.

1-0

LOW SPEED ENABLE

R/W

Enables low speed operation in 1-wire and 2-wire mode.

Depending upon sampling frequency, write this bit as per

Table 21.

Table 21. LOW SPEED ENABLE Register Settings Across fS

fS, MSPS

MIN

MAX

1-WIRE MODE

2-WIRE MODE

125

Not supported

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