ADC3421 datasheet(47/80 Pages) TI2

47 / 80 page

Frequency (MHz)

12.5

37.5

62.5

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

D201

Frequency (MHz)

12.5

37.5

62.5

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

D202

ADC3421, ADC3422, ADC3423, ADC3424

www.ti.com

SBAS673A – JULY 2014 – REVISED OCTOBER 2015

9.4.4 Internal Dither Algorithm

The ADC342x use an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither

algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm

can be turned off by using the DIS DITH CHx registers bits. Figure 141 and Figure 142 show the effect of using

dither algorithms.

SFDR = 95 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS,

SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS,

THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc

THD = 86 dBc, HD2 = 92 dBc, HD3 = 91 dBc

Figure 141. FFT for 10-MHz Input Signal

Figure 142. FFT for 10-MHz Input Signal

(Chopper On, Dither On)

(Chopper On, Dither Off)

9.4.5 Summary of Performance Mode Registers

Table 5 lists the location, value, and functions of performance mode registers in the device.

Table 5. Performance Modes

MODE

DESCRIPTION

Special modes

Registers 139 (bit 3), 239 (bit 3), 439 (bit 3), and 539 (bit 3)

Always write 1 for best performance

Registers 1 (bits 7:0), 134 (bits 5 and 3), 234 (bits 5 and 3),

Disable dither

Disable dither to improve SNR

434 (bits 5 and 3), and 534 (bits 5 and 3)

Disable chopper

Registers 122 (bit 1), 222 (bit 1), 422 (bit 1), and 522 (bit 1)

Disable chopper (shifts 1/f noise floor at dc)

Registers 11Dh (bit 1), 21Dh (bit 1), 41Dh (bit 1), 51Dh (bit 1),

High IF modes

Improves HD3 by a couple of dB for IF > 100 MHz

308h (bits 7-6) and 608h (bits 7-6)

9.5 Programming

The ADC342x can be configured using a serial programming interface, as described in this section.

9.5.1 Serial Interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data

output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at

every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th

SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are

ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can

function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50%

SCLK duty cycle.

Submit Documentation Feedback

Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424

ADC3421 Datasheet(PDF) 47 Page - Texas Instruments

ADC3421 Datasheet(HTML) 47 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL