ADC3421 datasheet(44/80 Pages) TI2

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Input Frequency (MHz)

100

1000

65.0

65.5

66.0

66.5

67.0

67.5

68.0

68.5

69.0

69.5

70.0

70.5

71.0

D001

D036

Ext Clock Jitter

35 fs

50 fs

100 fs

150 fs

200 fs

)

(

)

(

ADC

Aperture

Input

Clock

Ext

Jitter

ADC3421, ADC3422, ADC3423, ADC3424

SBAS673A – JULY 2014 – REVISED OCTOBER 2015

www.ti.com

The total clock jitter (TJitter) has two components: the internal aperture jitter (130 fs for the device) which is set by

the noise of the clock input buffer and the external clock. TJitter can be calculated with Equation 3.

(3)

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass

filters at the clock input; a faster clock slew rate improves the ADC aperture jitter. The devices have a typical

thermal noise of 72.7 dBFS and internal aperture jitter of 130 fs. The SNR, depending on the amount of external

jitter for different input frequencies, is shown in Figure 137.

Figure 137. SNR vs Frequency for Different Clock Jitter

9.3.3 Digital Output Interface

The devices offer two different output format options, thus making interfacing to a field-programmable gate array

(FPGA) or an application-specific integrated circuit (ASIC) easy. Each option can be easily programmed using

the serial interface, as shown in Table 3. The output interface options are:

•

One-wire, 1x frame clock, 12x serialization with the DDR bit clock and

•

Two-wire, 1x frame clock, 6x serialization with the DDR bit clock.

Table 3. Interface Rates

RECOMMENDED SAMPLING

BIT CLOCK

FRAME CLOCK

SERIAL DATA

INTERFACE

FREQUENCY (MSPS)

SERIALIZATION

FREQUENCY

RATE PER

OPTIONS

(MHz)

WIRE (Mbps)

MINIMUM

MAXIMUM

180

One-wire

12x

480

960

Two-wire

20(1)

120

(Default after

125

375

125

750

Reset)

(1)

Use the LOW SPEED ENABLE register bits for low speed operation; see Table 21.

9.3.3.1 One-Wire Interface: 12x Serialization

In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The

data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at

the rising edge of every frame clock, starting with the LSB. The data rate is 12x sample frequency (12x

serialization).

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